Participated in the ‘Feeding India’ , a campaign to create awareness, inspire and help economically weak peoples., Feeding India
Feb 2017 to Jul 2019

serving to free food to lower income people which are collected from restaurant/Hostels as wastage.

Attended event on "Robowars"- inter-college bot fight, SPICE society , JSSATE
Aug 2017 to Oct 2017

understand Robotics and Control System aspect of ROBOTS

Contributed on openSour RISC-V based processor called RVMyth, through the OpenFPGA framework , Skywater OpenSource FPGA (SOFA)., VLSI System Design | Skywater Technology inc., OpenFPGA
Jan 2023

Implemented complete FPGA flow using open-source tools like OpenFPGA having Basys3 board. Counter simulation and Elaboration, Synthesis, constraint, Counter implementation, VIO implementation VTR and VPR flows, Post-synthesis, Timing, Power analysis. RISC-V core programming using Vivado, RTL to synthesize up to bitstream generation. SOFA FPGA Fabric implementation andRISC-V core on custom SOFA fabric Link-https://github.com/abhi09v/FPGA---Fabric-Design-and-Architecture

Contribution on Advanced Physical Design using OpenLANE/Sky130, VLSI System Design | skywater technology inc
Feb 2023 to Present

Design and characterize your own standard cell. Have a hands-on in the Physical Design domain. Generate a full GDSII from a RTL netlist. Link- https://github.com/abhi09v/Advance-Physical-Design-RTL2GDS-using-OpenLane

Contributor of "Scripting in Synthesis and Design: AbhiSynth using TCL", VLSI System Design | efabless
Aug 2023

Created a unique User Interface(UI) AbhiSynth that takes RTL netlist & SDC constraints as inputs. Generate synthesized netlist and Pre-layout timing report as an output. It use Yosys Open source tool for synthesis and Opentimer to generate pre-layout timing reports Link- https://github.com/abhi09v/TCL-Scripting